Method for placing pins in integrated circuit layout design

The invention provides a method for placing pins in an integrated circuit layout design. The method comprises the following steps: 1) generating all pins of a circuit in a layout; 2) acquiring a signal line having the same line network information as the pin; the method comprises the steps of (1) obtaining a layout, (2) obtaining a layout boundary, (3) calculating the distance between the layout boundary and the tail end of a signal line, (5) determining the tail end, closest to the layout boundary, of the signal line as a drop point of the pin, and (6) adjusting the size and the process layer of the pin. 本发明提供了一种集成电路版图设计中摆放引脚的方法，包括以下步骤：1）在版图中生成电路的所有引脚；2）获取和引脚有相同线网信息的信号线；3）获取版图的边界；4）计算版图的边界和信号线末端的距离；5）确定距离版图的边界最近的信号线的末端作为引脚的落点；6）调整引脚的大小和工艺层。本发明可以实现自动摆放引脚，提高集成电路版图工程师的设计效率。