Packaging substrate for stacking, stacked packaging substrate, chip packaging structure of stacked packaging substrate, and preparation method of stacked packaging substrate
The invention discloses a stacked package substrate, which comprises a first package substrate and a second package substrate which are conductively jointed with each other, and is characterized in that the first package substrate comprises a first wiring layer, a first joint dielectric layer locate...
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creator | LUO FUMING LI ZONGYI GUO LIANGKUI LIANG XINFU |
description | The invention discloses a stacked package substrate, which comprises a first package substrate and a second package substrate which are conductively jointed with each other, and is characterized in that the first package substrate comprises a first wiring layer, a first joint dielectric layer located on the lower surface of the first wiring layer and a first joint conductive column surrounded by the first joint dielectric layer; the second packaging substrate comprises a second wiring layer, a second joint dielectric layer located on the upper surface of the second wiring layer and a second joint conductive column surrounded by the second joint dielectric layer; the first joint conductive columns and the second joint conductive columns correspondingly form conductive joint; the first bonding dielectric layer and the second bonding dielectric layer are physically bonded to form a bonding dielectric layer. The invention further discloses a packaging substrate for stacking, a chip packaging structure of the stac |
format | Patent |
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The invention further discloses a packaging substrate for stacking, a chip packaging structure of the stac</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230414&DB=EPODOC&CC=CN&NR=115966565A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230414&DB=EPODOC&CC=CN&NR=115966565A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LUO FUMING</creatorcontrib><creatorcontrib>LI ZONGYI</creatorcontrib><creatorcontrib>GUO LIANGKUI</creatorcontrib><creatorcontrib>LIANG XINFU</creatorcontrib><title>Packaging substrate for stacking, stacked packaging substrate, chip packaging structure of stacked packaging substrate, and preparation method of stacked packaging substrate</title><description>The invention discloses a stacked package substrate, which comprises a first package substrate and a second package substrate which are conductively jointed with each other, and is characterized in that the first package substrate comprises a first wiring layer, a first joint dielectric layer located on the lower surface of the first wiring layer and a first joint conductive column surrounded by the first joint dielectric layer; the second packaging substrate comprises a second wiring layer, a second joint dielectric layer located on the upper surface of the second wiring layer and a second joint conductive column surrounded by the second joint dielectric layer; the first joint conductive columns and the second joint conductive columns correspondingly form conductive joint; the first bonding dielectric layer and the second bonding dielectric layer are physically bonded to form a bonding dielectric layer. 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language | chi ; eng |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Packaging substrate for stacking, stacked packaging substrate, chip packaging structure of stacked packaging substrate, and preparation method of stacked packaging substrate |
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