EARC control method and device based on FPGA

The invention discloses an EARC control method and system based on an FPGA, IP cores of FPGA chips of an audio sending end and an audio receiving end are respectively obtained, MCU soft cores are respectively generated based on the IP cores, and the MCU soft cores are responsible for configuration and control actions of the EARC chips; the FPGA chip based on the audio sending end carries out audio data coding and packaging and sends the audio data to the Ethernet PHY chip so as to carry out long-distance transmission of the audio data based on the Ethernet PHY chip; and the PHY chip of the audio receiving end receives the signal transmitted by the network and sends the signal to the FPGA logic part of the receiving end for unpacking and decoding actions, the control data and the audio data are restored, and the output rate of the audio data is controlled based on the clock chip. Compared with the prior art, resources are divided in the FPGA to serve as an MCU soft core, the EARC chip is controlled and configu