Semi-parallel prospective SC decoder design method and system

The invention discloses a semi-parallel prospective SC decoder design method and system. The system comprises a control module, an LLR processing module, a partial sum module and a decoding output module. The method comprises the following steps: the LLR processing module receives LLR, and the decoder updates a decoding instruction; the LLR processing module carries out operation on LLR according to the decoding instruction and obtains a decoding result; the decoder stores the obtained decoding result and updates the partial sum module according to the decoding result; and the LLR processing module uses the updated partial sum module to continue decoding, and the decoding output module outputs a result after the decoding is finished. The delay of the semi-parallel SC decoder is reduced by introducing the prospective G operation, and the implementation efficiency of hardware is improved. 本发明公开了一种半并行的前瞻性SC译码器设计方法与系统，其中系统包括控制模块、LLR处理模块、部分和模块和译码输出模块；方法包括：LLR处理模块接收LLR，译码器更新译码指令；LLR处理模块根据译码指令对LLR进行运算，并得到译码结果；译码器保存得