RISC-V architecture-based ZUC algorithm implementation method, coprocessor and arithmetic device

The invention discloses a ZUC algorithm implementation method based on an RISC-V architecture, a coprocessor and an arithmetic device, and belongs to the technical field of ZUC algorithm implementation. According to the method, the RISC-V extended instruction set is added into the hardware logic structure of the processor by utilizing the characteristics of high operation speed and high software programming flexibility of the hardware logic structure, so that the processor can call the extended instruction set at the instruction set level; therefore, the execution capability of the processor on the ZUM algorithm is improved on the basis of increasing the richness of the instruction set of the processor. The RISC-V extended instruction set oriented to the ZUC algorithm provided by the invention has good flexibility, and developers can decide whether to add the extended instruction set into the hardware logic structure of the processor or not according to whether the requirement for the ZUC algorithm exists or