Low latency digital signature processing with side channel security

Low latency digital signatures with side channel security are described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing number-theoretical transform (NTT) and INTT (inverse NTT) processes; and one or more auxiliary operating circuits coupled with the coefficient multiplier circuit, each of the one or more auxiliary operating circuits performing an operation based at least in part on a result of the operation of the NTT/INTT coefficient multiplier circuit, one or more auxiliary operation circuits receive results of operation of the NTT/INTT coefficient multiplier circuit before the results are stored in the memory. 描述了具有侧信道安全性的低时延数字签名。装置的示例包括：系数乘法器电路，用于执行多项式乘法，系数乘法器电路提供数论变换(NTT)和INTT(逆NTT)处理；和与系数乘法器电路耦合的一个或多个辅助操作电路，一个或多个辅助操作电路中的每一个至少部分地基于NTT/INTT系数乘法器电路的操作的结果来执行运算，其中，一个或多个辅助操作电路在NTT/INTT系数乘法器电路的操作的结果被存储在存储器中之前，接收这些结果。