Comprehensive signal test platform and test method

The invention relates to the field of signal testing, in particular to a signal testing platform used for FPGA program testing and based on an ARM and an FPGA and a corresponding comprehensive signal testing method, random original data are generated at the ARM end in a multi-thread mode and sent to...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHEN XUAN, KANG JING, HU WANRU, WANG JING, ZHAO WEICHEN, LIU DI, MEI RURU, WANG ZHUGANG
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHEN XUAN
KANG JING
HU WANRU
WANG JING
ZHAO WEICHEN
LIU DI
MEI RURU
WANG ZHUGANG
description The invention relates to the field of signal testing, in particular to a signal testing platform used for FPGA program testing and based on an ARM and an FPGA and a corresponding comprehensive signal testing method, random original data are generated at the ARM end in a multi-thread mode and sent to the FPGA, the random original data are processed through a program to be tested on an FPGA platform and pass through an AWGN Gaussian white noise channel, and the random original data are transmitted to the FPGA. And a test result is transmitted back to the ARM end, so that the frame error rate and bit error rate test of a large data volume is realized. Meanwhile, through joint flow control of the ARM end and the FPGA end, it is guaranteed that the system transmits data at the maximum rate under the condition that data are not lost; and the ARM end divides original data sending and decoding result receiving into two threads, so that the idle time of the ARM can be greatly reduced, and the working efficiency of the
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115827440A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115827440A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115827440A3</originalsourceid><addsrcrecordid>eNrjZDByzs8tKErNSM0rzixLVSjOTM9LzFEoSS0uUSjISSxJyy_KVUjMS4GI5KaWZOSn8DCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_Q0NTCyNzExMDR2Ni1AAA6fssSA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Comprehensive signal test platform and test method</title><source>esp@cenet</source><creator>CHEN XUAN ; KANG JING ; HU WANRU ; WANG JING ; ZHAO WEICHEN ; LIU DI ; MEI RURU ; WANG ZHUGANG</creator><creatorcontrib>CHEN XUAN ; KANG JING ; HU WANRU ; WANG JING ; ZHAO WEICHEN ; LIU DI ; MEI RURU ; WANG ZHUGANG</creatorcontrib><description>The invention relates to the field of signal testing, in particular to a signal testing platform used for FPGA program testing and based on an ARM and an FPGA and a corresponding comprehensive signal testing method, random original data are generated at the ARM end in a multi-thread mode and sent to the FPGA, the random original data are processed through a program to be tested on an FPGA platform and pass through an AWGN Gaussian white noise channel, and the random original data are transmitted to the FPGA. And a test result is transmitted back to the ARM end, so that the frame error rate and bit error rate test of a large data volume is realized. Meanwhile, through joint flow control of the ARM end and the FPGA end, it is guaranteed that the system transmits data at the maximum rate under the condition that data are not lost; and the ARM end divides original data sending and decoding result receiving into two threads, so that the idle time of the ARM can be greatly reduced, and the working efficiency of the</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230321&amp;DB=EPODOC&amp;CC=CN&amp;NR=115827440A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230321&amp;DB=EPODOC&amp;CC=CN&amp;NR=115827440A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN XUAN</creatorcontrib><creatorcontrib>KANG JING</creatorcontrib><creatorcontrib>HU WANRU</creatorcontrib><creatorcontrib>WANG JING</creatorcontrib><creatorcontrib>ZHAO WEICHEN</creatorcontrib><creatorcontrib>LIU DI</creatorcontrib><creatorcontrib>MEI RURU</creatorcontrib><creatorcontrib>WANG ZHUGANG</creatorcontrib><title>Comprehensive signal test platform and test method</title><description>The invention relates to the field of signal testing, in particular to a signal testing platform used for FPGA program testing and based on an ARM and an FPGA and a corresponding comprehensive signal testing method, random original data are generated at the ARM end in a multi-thread mode and sent to the FPGA, the random original data are processed through a program to be tested on an FPGA platform and pass through an AWGN Gaussian white noise channel, and the random original data are transmitted to the FPGA. And a test result is transmitted back to the ARM end, so that the frame error rate and bit error rate test of a large data volume is realized. Meanwhile, through joint flow control of the ARM end and the FPGA end, it is guaranteed that the system transmits data at the maximum rate under the condition that data are not lost; and the ARM end divides original data sending and decoding result receiving into two threads, so that the idle time of the ARM can be greatly reduced, and the working efficiency of the</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDByzs8tKErNSM0rzixLVSjOTM9LzFEoSS0uUSjISSxJyy_KVUjMS4GI5KaWZOSn8DCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_Q0NTCyNzExMDR2Ni1AAA6fssSA</recordid><startdate>20230321</startdate><enddate>20230321</enddate><creator>CHEN XUAN</creator><creator>KANG JING</creator><creator>HU WANRU</creator><creator>WANG JING</creator><creator>ZHAO WEICHEN</creator><creator>LIU DI</creator><creator>MEI RURU</creator><creator>WANG ZHUGANG</creator><scope>EVB</scope></search><sort><creationdate>20230321</creationdate><title>Comprehensive signal test platform and test method</title><author>CHEN XUAN ; KANG JING ; HU WANRU ; WANG JING ; ZHAO WEICHEN ; LIU DI ; MEI RURU ; WANG ZHUGANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115827440A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN XUAN</creatorcontrib><creatorcontrib>KANG JING</creatorcontrib><creatorcontrib>HU WANRU</creatorcontrib><creatorcontrib>WANG JING</creatorcontrib><creatorcontrib>ZHAO WEICHEN</creatorcontrib><creatorcontrib>LIU DI</creatorcontrib><creatorcontrib>MEI RURU</creatorcontrib><creatorcontrib>WANG ZHUGANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN XUAN</au><au>KANG JING</au><au>HU WANRU</au><au>WANG JING</au><au>ZHAO WEICHEN</au><au>LIU DI</au><au>MEI RURU</au><au>WANG ZHUGANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Comprehensive signal test platform and test method</title><date>2023-03-21</date><risdate>2023</risdate><abstract>The invention relates to the field of signal testing, in particular to a signal testing platform used for FPGA program testing and based on an ARM and an FPGA and a corresponding comprehensive signal testing method, random original data are generated at the ARM end in a multi-thread mode and sent to the FPGA, the random original data are processed through a program to be tested on an FPGA platform and pass through an AWGN Gaussian white noise channel, and the random original data are transmitted to the FPGA. And a test result is transmitted back to the ARM end, so that the frame error rate and bit error rate test of a large data volume is realized. Meanwhile, through joint flow control of the ARM end and the FPGA end, it is guaranteed that the system transmits data at the maximum rate under the condition that data are not lost; and the ARM end divides original data sending and decoding result receiving into two threads, so that the idle time of the ARM can be greatly reduced, and the working efficiency of the</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN115827440A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Comprehensive signal test platform and test method
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T01%3A14%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHEN%20XUAN&rft.date=2023-03-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN115827440A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true