Internal clock signaling

The invention relates to internal clock signaling. A method includes selecting a particular R/B # pin among a plurality of ready/busy pins R/B # associated with a respective memory die among a plurality of memory dies of a memory device. The method further includes receiving, by at least one memory die among the plurality of memory dies, signaling indicating performance of a memory access while the particular R/B # pin is set to be low; and initiating an internal timing signal after receiving the signaling indicating execution of the memory access, where the internal timing signal is associated with a timing of operations performed by the plurality of memory dies. 本申请涉及内部时钟信令。一种方法包含在与存储器装置的多个存储器裸片当中的相应存储器裸片相关联的多个就绪/忙碌引脚R/B#当中选择特定的R/B#引脚。所述方法进一步包含在所述特定的R/B#引脚被设定为低的同时，通过所述多个存储器裸片当中的至少一个存储器裸片来接收指示存储器存取的执行的信令；以及在接收到指示所述存储器存取的执行的所述信令之后，起始内部定时信号，其中所述内部定时信号与由所述多个存储器裸片执行的操作的时序相关联。