Multi-stack semiconductor device with vertical misalignment and method of forming same

A multi-stack semiconductor device includes a lower stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, the lower gate structure surrounding the lower channel structure; an upper stacked transistor structure vertically stacked over the lower stacked transistor structure and including an upper active region including an upper channel structure and an upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, where the lower gate structure and the upper gate structure have substantially the same size in plan view, and where the lower gate structure does not completely overlap the upper gate structure in the vertical direction. 一种多堆叠半导体器件，包括：下堆叠晶体管结构，包括下有源区和下栅极结构，下有源区包括下沟道结构，下栅极结构围绕下沟道结构；上堆叠晶体管结构，垂直堆叠在下堆叠晶体管结构之上，并且包括上有源区和上栅极结构，上有源区包括上沟道结构，上栅极结构围绕上沟道结构；至少一个栅极接触插塞，接触下栅极结构的顶表面，其中下栅极结构和上栅极结构在平面图中具有基本相同的尺寸，并且其中下栅极结构在垂直方向上不与上栅极结构完全重叠