Memory device and memory test circuit and method with repair signal maintenance mechanism thereof

The invention provides a memory test circuit with a repair signal maintenance mechanism. The repair control circuit controls a memory built-in self-repair circuit to carry out a built-in self-repair program on a memory circuit, and comprises a remapping temporary storage circuit and a latch temporary storage circuit. After the built-in self-repairing program is completed, the remapping temporary storage circuit receives a repairing signal generated by the built-in self-repairing circuit of the memory and temporarily stores the repairing signal. The latch register circuit is electrically coupled between the remapping register circuit and a remapping circuit corresponding to the memory circuit, and receives and stores the repair signal from the remapping register circuit, so that when the remapping register circuit performs a scan test according to a scan chain, the remapping circuit accesses the repair signal, and the memory circuit performs a scan test according to the scan chain. And repairing the memory cir