Method for adjacently arranging multi-core chips
The invention discloses a method for adjacently arranging a multi-core chip, which comprises the following steps of: S1, grouping signal lines, analyzing input and output port signal lines of each single core, and grouping according to a function design and a topological structure; s2, topological c...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | The invention discloses a method for adjacently arranging a multi-core chip, which comprises the following steps of: S1, grouping signal lines, analyzing input and output port signal lines of each single core, and grouping according to a function design and a topological structure; s2, topological change: carrying out topological change on internal and top layer connecting lines of the single core, and adding decoding logic; s3, a buffer and a low-power-consumption unit are inserted, and the buffer and the low-power-consumption unit are added according to constraint conditions including a time sequence and low power consumption; and S4, physical implementation: implementing an adjacent layout and hierarchical physical implementation method. The topological structures of the single cores and the top layer signal lines are transformed, most inter-core connecting lines are eliminated, the effect of adjacent layout can be achieved, the congestion of the inter-core connecting lines and the corresponding area, powe |
---|