Chip diode packaging process

The invention provides a surface-mounted diode packaging process which comprises the following steps: S1, a plurality of columns of positive and negative electrode pin groups are arranged in a frame, positive and negative electrode pins of each column of pin group are oppositely arranged, a gap is a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HAN YUZHUAN, HAN XUEXIA, PENG WEIJUN, SONG JIANFENG
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator HAN YUZHUAN
HAN XUEXIA
PENG WEIJUN
SONG JIANFENG
description The invention provides a surface-mounted diode packaging process which comprises the following steps: S1, a plurality of columns of positive and negative electrode pin groups are arranged in a frame, positive and negative electrode pins of each column of pin group are oppositely arranged, a gap is arranged between the positive and negative electrode pins to form a partition, and a certain distance is reserved between each two pin groups; and S2, sequentially and fixedly adhering the first layer of solder paste, the chip and the second layer of solder paste on the positive electrode pin. And S3, installing a jump piece, adhering one end of the jump piece to the second layer of solder paste, and adhering the other end of the jump piece to the cathode pin through the solder paste, thereby realizing bridging connection of the anode pin and the cathode pin. And S4, the frame is transferred to a tunnel furnace to be welded. And S5, punching the welded frame, and after the welded single diode is punched down, leavin
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115602548A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115602548A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115602548A3</originalsourceid><addsrcrecordid>eNrjZJBxzsgsUEjJzE9JVShITM5OTM_MS1coKMpPTi0u5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcVA9al5qSXxzn6GhqZmBkamJhaOxsSoAQCI-SOQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Chip diode packaging process</title><source>esp@cenet</source><creator>HAN YUZHUAN ; HAN XUEXIA ; PENG WEIJUN ; SONG JIANFENG</creator><creatorcontrib>HAN YUZHUAN ; HAN XUEXIA ; PENG WEIJUN ; SONG JIANFENG</creatorcontrib><description>The invention provides a surface-mounted diode packaging process which comprises the following steps: S1, a plurality of columns of positive and negative electrode pin groups are arranged in a frame, positive and negative electrode pins of each column of pin group are oppositely arranged, a gap is arranged between the positive and negative electrode pins to form a partition, and a certain distance is reserved between each two pin groups; and S2, sequentially and fixedly adhering the first layer of solder paste, the chip and the second layer of solder paste on the positive electrode pin. And S3, installing a jump piece, adhering one end of the jump piece to the second layer of solder paste, and adhering the other end of the jump piece to the cathode pin through the solder paste, thereby realizing bridging connection of the anode pin and the cathode pin. And S4, the frame is transferred to a tunnel furnace to be welded. And S5, punching the welded frame, and after the welded single diode is punched down, leavin</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230113&amp;DB=EPODOC&amp;CC=CN&amp;NR=115602548A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230113&amp;DB=EPODOC&amp;CC=CN&amp;NR=115602548A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HAN YUZHUAN</creatorcontrib><creatorcontrib>HAN XUEXIA</creatorcontrib><creatorcontrib>PENG WEIJUN</creatorcontrib><creatorcontrib>SONG JIANFENG</creatorcontrib><title>Chip diode packaging process</title><description>The invention provides a surface-mounted diode packaging process which comprises the following steps: S1, a plurality of columns of positive and negative electrode pin groups are arranged in a frame, positive and negative electrode pins of each column of pin group are oppositely arranged, a gap is arranged between the positive and negative electrode pins to form a partition, and a certain distance is reserved between each two pin groups; and S2, sequentially and fixedly adhering the first layer of solder paste, the chip and the second layer of solder paste on the positive electrode pin. And S3, installing a jump piece, adhering one end of the jump piece to the second layer of solder paste, and adhering the other end of the jump piece to the cathode pin through the solder paste, thereby realizing bridging connection of the anode pin and the cathode pin. And S4, the frame is transferred to a tunnel furnace to be welded. And S5, punching the welded frame, and after the welded single diode is punched down, leavin</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJBxzsgsUEjJzE9JVShITM5OTM_MS1coKMpPTi0u5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcVA9al5qSXxzn6GhqZmBkamJhaOxsSoAQCI-SOQ</recordid><startdate>20230113</startdate><enddate>20230113</enddate><creator>HAN YUZHUAN</creator><creator>HAN XUEXIA</creator><creator>PENG WEIJUN</creator><creator>SONG JIANFENG</creator><scope>EVB</scope></search><sort><creationdate>20230113</creationdate><title>Chip diode packaging process</title><author>HAN YUZHUAN ; HAN XUEXIA ; PENG WEIJUN ; SONG JIANFENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115602548A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HAN YUZHUAN</creatorcontrib><creatorcontrib>HAN XUEXIA</creatorcontrib><creatorcontrib>PENG WEIJUN</creatorcontrib><creatorcontrib>SONG JIANFENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HAN YUZHUAN</au><au>HAN XUEXIA</au><au>PENG WEIJUN</au><au>SONG JIANFENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Chip diode packaging process</title><date>2023-01-13</date><risdate>2023</risdate><abstract>The invention provides a surface-mounted diode packaging process which comprises the following steps: S1, a plurality of columns of positive and negative electrode pin groups are arranged in a frame, positive and negative electrode pins of each column of pin group are oppositely arranged, a gap is arranged between the positive and negative electrode pins to form a partition, and a certain distance is reserved between each two pin groups; and S2, sequentially and fixedly adhering the first layer of solder paste, the chip and the second layer of solder paste on the positive electrode pin. And S3, installing a jump piece, adhering one end of the jump piece to the second layer of solder paste, and adhering the other end of the jump piece to the cathode pin through the solder paste, thereby realizing bridging connection of the anode pin and the cathode pin. And S4, the frame is transferred to a tunnel furnace to be welded. And S5, punching the welded frame, and after the welded single diode is punched down, leavin</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN115602548A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Chip diode packaging process
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T14%3A19%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HAN%20YUZHUAN&rft.date=2023-01-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN115602548A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true