Implementing pooling and anti-pooling or reverse pooling in hardware
Pooling and anti-pooling or reverse pooling are performed in hardware. A mechanism for processing data according to a neural network process on a hardware accelerator including fixed function circuitry, the neural network process including pooling, anti-pooling, or reverse pooling and/or binary argm...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | Pooling and anti-pooling or reverse pooling are performed in hardware. A mechanism for processing data according to a neural network process on a hardware accelerator including fixed function circuitry, the neural network process including pooling, anti-pooling, or reverse pooling and/or binary argmax/argmin functions. The function is mapped to a set of basic neural network operations that can be used by the fixed function circuitry. The neural network process is then performed using the fixed function circuitry. The data processed using the neural network process includes image and/or audio data.
在硬件中实施池化和反池化或反向池化。一种用于在包括固定功能电路系统的硬件加速器上根据神经网络过程来处理数据的机制,所述神经网络过程包括池化、反池化或反向池化和/或二进制argmax/argmin函数。将所述函数映射到能够供所述固定功能电路系统使用的基本神经网络运算集合。随后使用所述固定功能电路系统执行所述神经网络过程。使用所述神经网络过程处理的所述数据包括图像和/或音频数据。 |
---|