Modeling method of MOS transistor mismatch model
The invention provides a modeling method of an MOS transistor mismatch model. The modeling method comprises the steps that S1, the mismatch value of a pair of MOS transistors is tested; s2, establishing a relational expression between the mismatch value and the channel length and the channel width o...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention provides a modeling method of an MOS transistor mismatch model. The modeling method comprises the steps that S1, the mismatch value of a pair of MOS transistors is tested; s2, establishing a relational expression between the mismatch value and the channel length and the channel width of the MOS transistor; s3, circulating the step S1 to the step S2 to obtain a relational expression between the mismatch values of the multiple pairs of MOS transistors and the channel lengths and the channel widths of the MOS transistors; and S4, fitting is performed according to the actual mismatch value obtained by testing each pair of MOS transistors and the relational expression, so that a mismatch model of the MOS transistors can be obtained. Compared with the prior art, the modeling method of the MOS transistor mismatch model has the advantage that the MOS transistor mismatch model with higher precision can be obtained.
本发明提供了一种MOS晶体管失配模型的建模方法,包括:步骤S1:测试一对MOS晶体管的失配值;步骤S2:建立所述失配值与所述MOS晶体管的沟道长度和沟道宽度之间的关系式;步骤S3: |
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