Parallel decoding method, processor, chip and electronic equipment

The embodiment of the invention provides a parallel decoding method, a processor, a chip and electronic equipment, the processor at least comprises a first decoder group and a second decoder group, and the second decoder group is provided with at least one shared decoder shared by the first decoder group; the method comprises the following steps: selecting a plurality of instructions from a first instruction queue corresponding to a first decoder group; if the number of the plurality of instructions is greater than the number of decoders in the first decoder group, allocating a first instruction, corresponding to the number of the decoders in the first decoder group, in the plurality of instructions to the decoders in the first decoder group for decoding, and allocating a second instruction except the first instruction in the plurality of instructions to a shared decoder for decoding; and writing a microinstruction obtained by decoding the first instruction by the first decoder group and a microinstruction ob