System and method for low phase error clock recovery for NFC transceivers
A card clock recovery system for use in an NFC card transceiver is disclosed, wherein the NFC card transceiver may be coupled to an NFC reader. The card clock recovery system has a phase-locked loop having a phase/frequency detector configured to receive a reference signal provided at the RX port of...
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| creator | GUETTEN OLIVER FREDERICK JAMIN OLIVIER JEROME CELESTINE SUSPLUGAS, OLIVER |
| description | A card clock recovery system for use in an NFC card transceiver is disclosed, wherein the NFC card transceiver may be coupled to an NFC reader. The card clock recovery system has a phase-locked loop having a phase/frequency detector configured to receive a reference signal provided at the RX port of the matching network during a receive mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmit mode of the NFC transceiver, receiving the loop feedback signal and providing a phase error signal representing a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal derived from the phase error signal and to provide a filtered corrected phase error signal; and a controllable oscillator configured to receive the filtered corrected phase error signal and provide a controlled frequency output signal. The card clock recovery system additionally has a phase offset co |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115498996A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115498996A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115498996A3</originalsourceid><addsrcrecordid>eNrjZPAMriwuSc1VSMxLUchNLcnIT1FIyy9SyMkvVyjISCxOVUgtKgLyk3Pyk7MVilKT88tSiyrBSvzcnBVKihLzipNTM4GCxTwMrGmJOcWpvFCam0HRzTXE2UM3tSA_PrW4IDE5NS-1JN7Zz9DQ1MTSwtLSzNGYGDUAs8g0dw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>System and method for low phase error clock recovery for NFC transceivers</title><source>esp@cenet</source><creator>GUETTEN OLIVER FREDERICK ; JAMIN OLIVIER JEROME CELESTINE ; SUSPLUGAS, OLIVER</creator><creatorcontrib>GUETTEN OLIVER FREDERICK ; JAMIN OLIVIER JEROME CELESTINE ; SUSPLUGAS, OLIVER</creatorcontrib><description>A card clock recovery system for use in an NFC card transceiver is disclosed, wherein the NFC card transceiver may be coupled to an NFC reader. The card clock recovery system has a phase-locked loop having a phase/frequency detector configured to receive a reference signal provided at the RX port of the matching network during a receive mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmit mode of the NFC transceiver, receiving the loop feedback signal and providing a phase error signal representing a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal derived from the phase error signal and to provide a filtered corrected phase error signal; and a controllable oscillator configured to receive the filtered corrected phase error signal and provide a controlled frequency output signal. The card clock recovery system additionally has a phase offset co</description><language>chi ; eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221220&DB=EPODOC&CC=CN&NR=115498996A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221220&DB=EPODOC&CC=CN&NR=115498996A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GUETTEN OLIVER FREDERICK</creatorcontrib><creatorcontrib>JAMIN OLIVIER JEROME CELESTINE</creatorcontrib><creatorcontrib>SUSPLUGAS, OLIVER</creatorcontrib><title>System and method for low phase error clock recovery for NFC transceivers</title><description>A card clock recovery system for use in an NFC card transceiver is disclosed, wherein the NFC card transceiver may be coupled to an NFC reader. The card clock recovery system has a phase-locked loop having a phase/frequency detector configured to receive a reference signal provided at the RX port of the matching network during a receive mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmit mode of the NFC transceiver, receiving the loop feedback signal and providing a phase error signal representing a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal derived from the phase error signal and to provide a filtered corrected phase error signal; and a controllable oscillator configured to receive the filtered corrected phase error signal and provide a controlled frequency output signal. The card clock recovery system additionally has a phase offset co</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAMriwuSc1VSMxLUchNLcnIT1FIyy9SyMkvVyjISCxOVUgtKgLyk3Pyk7MVilKT88tSiyrBSvzcnBVKihLzipNTM4GCxTwMrGmJOcWpvFCam0HRzTXE2UM3tSA_PrW4IDE5NS-1JN7Zz9DQ1MTSwtLSzNGYGDUAs8g0dw</recordid><startdate>20221220</startdate><enddate>20221220</enddate><creator>GUETTEN OLIVER FREDERICK</creator><creator>JAMIN OLIVIER JEROME CELESTINE</creator><creator>SUSPLUGAS, OLIVER</creator><scope>EVB</scope></search><sort><creationdate>20221220</creationdate><title>System and method for low phase error clock recovery for NFC transceivers</title><author>GUETTEN OLIVER FREDERICK ; JAMIN OLIVIER JEROME CELESTINE ; SUSPLUGAS, OLIVER</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115498996A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION</topic><toplevel>online_resources</toplevel><creatorcontrib>GUETTEN OLIVER FREDERICK</creatorcontrib><creatorcontrib>JAMIN OLIVIER JEROME CELESTINE</creatorcontrib><creatorcontrib>SUSPLUGAS, OLIVER</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GUETTEN OLIVER FREDERICK</au><au>JAMIN OLIVIER JEROME CELESTINE</au><au>SUSPLUGAS, OLIVER</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System and method for low phase error clock recovery for NFC transceivers</title><date>2022-12-20</date><risdate>2022</risdate><abstract>A card clock recovery system for use in an NFC card transceiver is disclosed, wherein the NFC card transceiver may be coupled to an NFC reader. The card clock recovery system has a phase-locked loop having a phase/frequency detector configured to receive a reference signal provided at the RX port of the matching network during a receive mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmit mode of the NFC transceiver, receiving the loop feedback signal and providing a phase error signal representing a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal derived from the phase error signal and to provide a filtered corrected phase error signal; and a controllable oscillator configured to receive the filtered corrected phase error signal and provide a controlled frequency output signal. The card clock recovery system additionally has a phase offset co</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION |
| title | System and method for low phase error clock recovery for NFC transceivers |
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