Novel Psum calculation circuit for convolutional neural network

The invention discloses a novel Psum calculation circuit for a convolutional neural network, which comprises a Psum memory, a read-write controller and an adder, and is characterized in that the Psum memory is formed by adopting a single-port SRAM (Static Random Access Memory), double data bit width is used, a read-write circuit and the adder are matched, one-time read-write operation and accumulation calculation can be carried out on each clock, and the area of the circuit is greatly reduced. The NPU in the convolutional neural network is generally provided with buffers (much larger than a Psum buffer in capacity) of an input feature map and an output feature map, the buffer of the output feature map is used as a buffer, the bit width of the Psum memory is set to be two times of the data bit width, a Psum calculation circuit with the same efficiency can be realized by adopting a read-write staggered control mode, and the Psum calculation circuit is simple in structure and convenient to operate. And an indepe