Time sequence path screening method and device

The invention provides a time sequence path screening method and device, and relates to the technical field of integrated circuits, and the method comprises the steps: determining a time sequence path related to a time sequence logic element corresponding to each clock port in a first list; and calculating a clock offset corresponding to each time sequence path, and determining whether each time sequence path has a time sequence violation risk according to the clock offset corresponding to each time sequence path and a preset clock offset threshold. According to the method and the device, the time sequence path with a time sequence violation risk caused by clock skew can be screened out, so that the yield of a chip is improved. 本申请提供一种时序路径筛查方法及设备，涉及集成电路技术领域，包括：确定与第一列表中的各个时钟端口对应的时序逻辑元件相关的时序路径；计算各个时序路径对应的时钟偏移，并根据各个时序路径对应的时钟偏移与预设时钟偏移阈值，确定各个时序路径是否存在时序违例风险。本申请可以筛查出因时钟偏移导致存在时序违例风险的时序路径，从而有利于提高芯片的良率。