Multi-matrix node bus topological structure based on RISC-V instruction set and working method thereof
The invention relates to a multi-matrix node bus topological structure based on an RISC-V instruction set and a working method of the multi-matrix node bus topological structure. The multi-matrix node bus topological structure comprises a high-speed bus matrix node, a plurality of slow-speed bus mat...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention relates to a multi-matrix node bus topological structure based on an RISC-V instruction set and a working method of the multi-matrix node bus topological structure. The multi-matrix node bus topological structure comprises a high-speed bus matrix node, a plurality of slow-speed bus matrix nodes and a plurality of low-speed bus matrix nodes. Each matrix node controls power consumption to form an efficiency difference through different widths, different working frequencies or different working voltages of bus channels, and a multi-stage working voltage mode is designed to meet the working mode of the same matrix node at different voltages or different working frequencies, so that the matrix nodes at the same stage can also be connected with each other, and the working efficiency of the matrix node is improved. And normal communication and working states are maintained. Meanwhile, internal nodes of each type of matrix nodes are designed, access permissions are determined according to different chan |
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