Four-emission RISC-V processor micro-architecture and working method thereof

The invention relates to a four-emission RISC-V processor micro-architecture and a working method thereof, and the four-emission RISC-V processor micro-architecture adopts a multi-emission structure, is divided into 12-14 stages of shaping assembly lines, and can be used as a high-performance assembly line architecture. In order to solve branch risks, a two-stage branch prediction architecture is adopted in the micro-architecture; an RISC-V instruction set is expanding and a plurality of long instructions appear, so that a decoding stage is divided into three simple decoders and one complex decoder, and the complex decoder is responsible for decoding the long instructions; a micro-operation queue is arranged behind a decoding stage and used for caching micro-operations of instructions decomposed by the decoding stage, the micro-operation queue provides five micro-operations for a post-stage assembly line in each period, the subsequent assembly line is the micro-operation queue, but each micro-operation has a