Integrated circuit and integrated circuit power switch synchronization noise test method

An integrated circuit and an integrated circuit power switch synchronization noise test method relate to the integrated circuit technology. A power switch synchronous noise test circuit is arranged in an integrated circuit chip. The power switch synchronous noise test circuit comprises a clock management and distribution circuit; a power switch of the tested power supply load circuit is controlled by the high-frequency clock module and the sampling circuit, a signal input end of the tested power supply load circuit is connected with the tested power supply load circuit, and a control end of the tested power supply load circuit is connected with the low-frequency clock module; and the input end of the digitization circuit is connected with the signal output end of the sampling circuit, and the output end of the digitization circuit is the output end of the power switch synchronous noise test circuit. According to the invention, the interference of factors such as chip packaging, a circuit board, peripheral dev