Operand pool instruction reservation cluster in scheduler circuitry in processor

The invention discloses an operand pool instruction reservation cluster in a scheduler circuit in a processor. The scheduler circuit includes a plurality of operand pool reservation circuits, each having an allocated number of source operands for a stored instruction that must be prepared prior to i...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	COSINDIN ARES VIRGINIA R, SMITH, ROBERT, W, PRIYADARSHI SUNIL, TEKMAN, YVONNE, C
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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