Operand pool instruction reservation cluster in scheduler circuitry in processor

The invention discloses an operand pool instruction reservation cluster in a scheduler circuit in a processor. The scheduler circuit includes a plurality of operand pool reservation circuits, each having an allocated number of source operands for a stored instruction that must be prepared prior to issuing the instruction. Instructions that have the same number of source operands but have not been ready to publish may be stored in operand pool reservation circuitry that has the same allocated number of source operands. In this manner, multiple reservation entries and associated comparator circuits in a cluster scheduler circuit are distributed among multiple operand pool reservation circuits to avoid or reduce an increase in the number and complexity of schedule path connections in each reservation circuit. This may avoid or reduce an increase in scheduling latency for a given number of reserved entries in the cluster scheduler circuit. 公开了处理器中的调度器电路中的操作数池指令预留集群。调度器电路包括多个操作数池预留电路，每个操作数池预留电路具有用于存储的指令的分配数目的源操作数，