Low latency storage based on data size

The invention relates to low latency storage based on data size. A memory system may include logic, a processor, a first memory, and a second memory. The logic may be configured to receive commands or data, or both, from a host system. The first memory and the second memory may be coupled with the processor. The processor may be configured to store data of a command associated with data less than a threshold in the first memory or to cause the data to be stored in the first memory, and to store data of a command associated with data greater than the threshold in the second memory. A first communication path between the logic and the first memory may be associated with a faster transfer speed than a second communication path between the logic and the second memory. 本申请涉及基于数据大小的低延迟存储。一种存储器系统可包含逻辑、处理器、第一存储器和第二存储器。所述逻辑可被配置成从主机系统接收命令或数据或这两者。所述第一存储器和所述第二存储器可与所述处理器耦合。所述处理器可被配置成将与小于阈值的数据相关联的命令的数据存储在所述第一存储器中或使所述数据存储在所述第一存储器中，并且将与大于所述阈值的数据相关联的命令的数据存储在所述第二存储器中。与所述逻辑与所述第二存储器之间的第二通信路径相比，所述逻辑与所述第一存储器之间的第一通信路径可与更快的传送速度相关联。