Time tracking circuit for FRAM
The invention discloses a time tracking circuit for an FRAM. Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit (100) includes a controller (102) that outputs a signal to an input of a driver (106, 108); a transistor (107, 109) coupled to an output...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | TOOPS DAVID J |
description | The invention discloses a time tracking circuit for an FRAM. Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit (100) includes a controller (102) that outputs a signal to an input of a driver (106, 108); a transistor (107, 109) coupled to an output of the driver (106, 108); a driver (106, 108) that outputs a first voltage to the transistor (107, 109) in response to the reception signal; and a transistor (107, 109) that outputs a second voltage to the bit cell (120) after a delay of the transistor in response to receiving the first voltage, the transistor (107, 109) being selected based on a size of the memory circuit (100).
本申请公开一种用于FRAM的时间跟踪电路。公开了用于读取和/或写入FRAM存储器的方法和设备。示例存储器电路(100)包括:控制器(102),其向驱动器(106、108)的输入端输出信号;晶体管(107、109),其耦合驱动器(106、108)的输出端;驱动器(106、108),其响应于接收信号,向晶体管(107、109)输出第一电压;以及晶体管(107、109),其响应于接收第一电压,在晶体管延迟之后向位单元(120)输出第二电压,晶体管(107、109)基于存储器电路(100)的尺寸被选择。 |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115295037A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115295037A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115295037A3</originalsourceid><addsrcrecordid>eNrjZJALycxNVSgpSkzOzsxLV0jOLEouzSxRSMsvUnALcvTlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhqZGlqYGxuaOxsSoAQC1wSPJ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Time tracking circuit for FRAM</title><source>esp@cenet</source><creator>TOOPS DAVID J</creator><creatorcontrib>TOOPS DAVID J</creatorcontrib><description>The invention discloses a time tracking circuit for an FRAM. Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit (100) includes a controller (102) that outputs a signal to an input of a driver (106, 108); a transistor (107, 109) coupled to an output of the driver (106, 108); a driver (106, 108) that outputs a first voltage to the transistor (107, 109) in response to the reception signal; and a transistor (107, 109) that outputs a second voltage to the bit cell (120) after a delay of the transistor in response to receiving the first voltage, the transistor (107, 109) being selected based on a size of the memory circuit (100).
本申请公开一种用于FRAM的时间跟踪电路。公开了用于读取和/或写入FRAM存储器的方法和设备。示例存储器电路(100)包括:控制器(102),其向驱动器(106、108)的输入端输出信号;晶体管(107、109),其耦合驱动器(106、108)的输出端;驱动器(106、108),其响应于接收信号,向晶体管(107、109)输出第一电压;以及晶体管(107、109),其响应于接收第一电压,在晶体管延迟之后向位单元(120)输出第二电压,晶体管(107、109)基于存储器电路(100)的尺寸被选择。</description><language>chi ; eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221104&DB=EPODOC&CC=CN&NR=115295037A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221104&DB=EPODOC&CC=CN&NR=115295037A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TOOPS DAVID J</creatorcontrib><title>Time tracking circuit for FRAM</title><description>The invention discloses a time tracking circuit for an FRAM. Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit (100) includes a controller (102) that outputs a signal to an input of a driver (106, 108); a transistor (107, 109) coupled to an output of the driver (106, 108); a driver (106, 108) that outputs a first voltage to the transistor (107, 109) in response to the reception signal; and a transistor (107, 109) that outputs a second voltage to the bit cell (120) after a delay of the transistor in response to receiving the first voltage, the transistor (107, 109) being selected based on a size of the memory circuit (100).
本申请公开一种用于FRAM的时间跟踪电路。公开了用于读取和/或写入FRAM存储器的方法和设备。示例存储器电路(100)包括:控制器(102),其向驱动器(106、108)的输入端输出信号;晶体管(107、109),其耦合驱动器(106、108)的输出端;驱动器(106、108),其响应于接收信号,向晶体管(107、109)输出第一电压;以及晶体管(107、109),其响应于接收第一电压,在晶体管延迟之后向位单元(120)输出第二电压,晶体管(107、109)基于存储器电路(100)的尺寸被选择。</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJALycxNVSgpSkzOzsxLV0jOLEouzSxRSMsvUnALcvTlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhqZGlqYGxuaOxsSoAQC1wSPJ</recordid><startdate>20221104</startdate><enddate>20221104</enddate><creator>TOOPS DAVID J</creator><scope>EVB</scope></search><sort><creationdate>20221104</creationdate><title>Time tracking circuit for FRAM</title><author>TOOPS DAVID J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115295037A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>TOOPS DAVID J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TOOPS DAVID J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Time tracking circuit for FRAM</title><date>2022-11-04</date><risdate>2022</risdate><abstract>The invention discloses a time tracking circuit for an FRAM. Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit (100) includes a controller (102) that outputs a signal to an input of a driver (106, 108); a transistor (107, 109) coupled to an output of the driver (106, 108); a driver (106, 108) that outputs a first voltage to the transistor (107, 109) in response to the reception signal; and a transistor (107, 109) that outputs a second voltage to the bit cell (120) after a delay of the transistor in response to receiving the first voltage, the transistor (107, 109) being selected based on a size of the memory circuit (100).
本申请公开一种用于FRAM的时间跟踪电路。公开了用于读取和/或写入FRAM存储器的方法和设备。示例存储器电路(100)包括:控制器(102),其向驱动器(106、108)的输入端输出信号;晶体管(107、109),其耦合驱动器(106、108)的输出端;驱动器(106、108),其响应于接收信号,向晶体管(107、109)输出第一电压;以及晶体管(107、109),其响应于接收第一电压,在晶体管延迟之后向位单元(120)输出第二电压,晶体管(107、109)基于存储器电路(100)的尺寸被选择。</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN115295037A |
source | esp@cenet |
subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | Time tracking circuit for FRAM |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T07%3A16%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TOOPS%20DAVID%20J&rft.date=2022-11-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN115295037A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |