Address optimization device for wafer level processor IIC configuration interface

The invention discloses an address optimization device for an IIC configuration interface of a wafer level processor, which comprises an IIC control module in a silicon substrate and a protocol conversion unit in a wafer processor power supply board, and is characterized in that the IIC control module in the silicon substrate is realized by using a transistor in the silicon substrate and comprises a redundancy module; a protocol conversion unit in the power supply board is a CPLD (Complex Programmable Logic Device) or FPGA (Field Programmable Gate Array) device, and an external interface controller, a protocol conversion module, an IIC (Inter-Integrated Circuit) main controller, a channel switching MUX (Multiplexer) and other modules are arranged in the protocol conversion unit. And the IIC clock and the data line are simplified, and the number of connecting channels between the wafer processor and the power supply system is greatly reduced, so that channel isolation is completed, the density of the connectin