Full-digital management device for wafer-level processor system

The invention discloses a full-digital management device for a wafer-level processor system, which realizes fine control on main functional units of the wafer-level processor system by using a programmable logic device, and provides an independent main controller and a physical channel for each unit by using the advantages of multiple pins and parallel processing of the programmable logic device, so as to realize full-digital management of the wafer-level processor system. High efficiency, high real-time management and fault isolation are realized, and normalization of slave addresses of all managed functional units with bus protocols is realized. In topology, a one-master multi-slave structure is formed by using a plurality of programmable logic devices, and the master and the slave are connected through a full-duplex high-speed interface, so that the expansion of management IO pins is realized. The master control unit and the slave expansion unit are installed on different layers of the power supply system,