Doped sidewall spacer/etch stop layer for memory

The invention relates to a doped sidewall spacer/etch stop layer for memory. Various embodiments of the present disclosure relate to an integrated circuit (IC) chip including a memory cell and having a sidewall spacer and/or an etch stop layer doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell includes a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. A sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and an etch stop layer is lined to the sidewall spacer. The sidewall spacer and the etch stop layer are in direct contact at the interface and form an electrical dipole at the interface. The doping for reducing charge accumulation reduces the electric field generated by the electric dipoles, thereby reducing the impact of the electric field on the memory cells. 本公开涉及用于存储器的掺杂的侧壁间隔件/蚀刻停止层。本公