Chip vertical integrated packaging structure using support plate and preparation method thereof

The invention discloses a chip vertical integrated packaging structure using a carrier plate and a preparation method thereof, and relates to the technical field of integrated circuit three-dimensional packaging, and the specific steps are as follows: preparing a copper column bump on a pad of a first chip, and preparing a tin bump on a pad of a second chip; exposing the conductive metal layer on any surface of the carrier plate based on the second chip; exposing the metal layer in the support plate on the other surface of the support plate by adopting a laser drilling method based on the first chip to form a first conductive blind hole; the first chip and the second chip are arranged on the two sides of the carrier plate according to different methods, and preparation of the packaging module is completed; according to the invention, highly integrated reliable packaging of chips with various sizes and different functions is realized through the carrier plate. 本发明公开了一种利用载板的芯片垂直集成封装结构及其制备方法，涉及集成电路三维封装技术领域，具体步骤为