Chip packaging structure and power device

The invention discloses a chip packaging structure and a power device. The chip packaging structure comprises a pin, a driving transistor and a chip, the source electrode of the chip is connected with the grid electrode of the driving transistor, and the grid electrode of the chip is connected with the source electrode of the driving transistor; the pins comprise a first pin, a second pin, a third pin and a fourth pin, the first pin is connected with the drain electrode of the chip, the second pin is connected with the source electrode of the driving transistor to form a power loop, the third pin is connected with the source electrode of the driving transistor, and the fourth pin is connected with the grid electrode of the driving transistor to form a driving loop. According to the invention, the parasitic inductance oscillation caused by the source shared by the driving loop and the power loop is avoided, so that the switching speed of the power device can be improved, and the conduction loss is reduced. 本申请