Chip packaging method and chip packaging structure

The invention provides a chip packaging method and a chip packaging structure, and relates to the field of semiconductor packaging. The chip packaging method is used for packaging a wafer and a substrate, one surface of the wafer is provided with a plurality of conductive bulge structures, one surface of the substrate is provided with welding pads corresponding to the plurality of conductive bulge structures, and the chip packaging method comprises the following steps: arranging conductive salient points on the plurality of welding pads of the substrate; arranging a conductive layer at one end, far away from the wafer, of each conductive bulge structure of the wafer; the conductive layer in the wafer and the corresponding conductive salient points on the substrate are welded to form the chip packaging structure, and in the chip packaging structure, the distance between the substrate and the wafer is larger than or equal to the preset distance, so that the spacing distance between the wafer and the substrate a