SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Embodiments relate to a semiconductor memory device and a method of manufacturing the same. According to one embodiment, a semiconductor memory device includes a substrate (20), a source line (SL), a plurality of word lines (WL), a pillar (MP), and a first member. The plurality of word lines (WL) ar...

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Hauptverfasser: IWASAKI TAICHI, FUJISHIMA TATSUYA, SHISHIDO MASAYUKI, KAJINO TOMONORI, KIDO NOZOMI
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ELECTRICITY
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creator IWASAKI TAICHI
FUJISHIMA TATSUYA
SHISHIDO MASAYUKI
KAJINO TOMONORI
KIDO NOZOMI
description Embodiments relate to a semiconductor memory device and a method of manufacturing the same. According to one embodiment, a semiconductor memory device includes a substrate (20), a source line (SL), a plurality of word lines (WL), a pillar (MP), and a first member. The plurality of word lines (WL) are provided above the source line (SL) so as to be separated from each other in a first direction intersecting the surface of the substrate (20). The pillar (MP) is provided so as to extend in the first direction. The bottom of the pillar (MP) reaches the source line (SL). The first member is provided so as to pass through the source line (SL). The first member has a first portion (UP) farther from the substrate (20) and a second portion (LP) closer to the substrate (20). The first member includes a first contact (CX) and a first insulating film (SP). The first contact (CX) is electrically connected to the substrate (20). The first insulating film (SP) is provided continuously with a side surface portion of the firs
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115117082A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115117082A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115117082A3</originalsourceid><addsrcrecordid>eNrjZLAJdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHZVcPRzUfB19At1c3QOCQ3y9HMHyod4-LsohHi4Brn6u_EwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknhnP0NDU0NDcwMLI0djYtQAAB8_KbQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>IWASAKI TAICHI ; FUJISHIMA TATSUYA ; SHISHIDO MASAYUKI ; KAJINO TOMONORI ; KIDO NOZOMI</creator><creatorcontrib>IWASAKI TAICHI ; FUJISHIMA TATSUYA ; SHISHIDO MASAYUKI ; KAJINO TOMONORI ; KIDO NOZOMI</creatorcontrib><description>Embodiments relate to a semiconductor memory device and a method of manufacturing the same. According to one embodiment, a semiconductor memory device includes a substrate (20), a source line (SL), a plurality of word lines (WL), a pillar (MP), and a first member. The plurality of word lines (WL) are provided above the source line (SL) so as to be separated from each other in a first direction intersecting the surface of the substrate (20). The pillar (MP) is provided so as to extend in the first direction. The bottom of the pillar (MP) reaches the source line (SL). The first member is provided so as to pass through the source line (SL). The first member has a first portion (UP) farther from the substrate (20) and a second portion (LP) closer to the substrate (20). The first member includes a first contact (CX) and a first insulating film (SP). The first contact (CX) is electrically connected to the substrate (20). The first insulating film (SP) is provided continuously with a side surface portion of the firs</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220927&amp;DB=EPODOC&amp;CC=CN&amp;NR=115117082A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220927&amp;DB=EPODOC&amp;CC=CN&amp;NR=115117082A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>IWASAKI TAICHI</creatorcontrib><creatorcontrib>FUJISHIMA TATSUYA</creatorcontrib><creatorcontrib>SHISHIDO MASAYUKI</creatorcontrib><creatorcontrib>KAJINO TOMONORI</creatorcontrib><creatorcontrib>KIDO NOZOMI</creatorcontrib><title>SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF</title><description>Embodiments relate to a semiconductor memory device and a method of manufacturing the same. According to one embodiment, a semiconductor memory device includes a substrate (20), a source line (SL), a plurality of word lines (WL), a pillar (MP), and a first member. The plurality of word lines (WL) are provided above the source line (SL) so as to be separated from each other in a first direction intersecting the surface of the substrate (20). The pillar (MP) is provided so as to extend in the first direction. The bottom of the pillar (MP) reaches the source line (SL). The first member is provided so as to pass through the source line (SL). The first member has a first portion (UP) farther from the substrate (20) and a second portion (LP) closer to the substrate (20). The first member includes a first contact (CX) and a first insulating film (SP). The first contact (CX) is electrically connected to the substrate (20). The first insulating film (SP) is provided continuously with a side surface portion of the firs</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAJdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHZVcPRzUfB19At1c3QOCQ3y9HMHyod4-LsohHi4Brn6u_EwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknhnP0NDU0NDcwMLI0djYtQAAB8_KbQ</recordid><startdate>20220927</startdate><enddate>20220927</enddate><creator>IWASAKI TAICHI</creator><creator>FUJISHIMA TATSUYA</creator><creator>SHISHIDO MASAYUKI</creator><creator>KAJINO TOMONORI</creator><creator>KIDO NOZOMI</creator><scope>EVB</scope></search><sort><creationdate>20220927</creationdate><title>SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF</title><author>IWASAKI TAICHI ; FUJISHIMA TATSUYA ; SHISHIDO MASAYUKI ; KAJINO TOMONORI ; KIDO NOZOMI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115117082A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>IWASAKI TAICHI</creatorcontrib><creatorcontrib>FUJISHIMA TATSUYA</creatorcontrib><creatorcontrib>SHISHIDO MASAYUKI</creatorcontrib><creatorcontrib>KAJINO TOMONORI</creatorcontrib><creatorcontrib>KIDO NOZOMI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>IWASAKI TAICHI</au><au>FUJISHIMA TATSUYA</au><au>SHISHIDO MASAYUKI</au><au>KAJINO TOMONORI</au><au>KIDO NOZOMI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF</title><date>2022-09-27</date><risdate>2022</risdate><abstract>Embodiments relate to a semiconductor memory device and a method of manufacturing the same. According to one embodiment, a semiconductor memory device includes a substrate (20), a source line (SL), a plurality of word lines (WL), a pillar (MP), and a first member. The plurality of word lines (WL) are provided above the source line (SL) so as to be separated from each other in a first direction intersecting the surface of the substrate (20). The pillar (MP) is provided so as to extend in the first direction. The bottom of the pillar (MP) reaches the source line (SL). The first member is provided so as to pass through the source line (SL). The first member has a first portion (UP) farther from the substrate (20) and a second portion (LP) closer to the substrate (20). The first member includes a first contact (CX) and a first insulating film (SP). The first contact (CX) is electrically connected to the substrate (20). The first insulating film (SP) is provided continuously with a side surface portion of the firs</abstract><oa>free_for_read</oa></addata></record>
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title SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T06%3A58%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=IWASAKI%20TAICHI&rft.date=2022-09-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN115117082A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true