Method and system for optimizing physical layout of integrated circuit device

A method and system for optimizing a physical layout of an integrated circuit device, the method in certain embodiments comprising: using a computer system that includes generating an EDA tool to generate a layout of the IC device; one or more input variable parameters, such as the size of the IC device and the size of a voltage region in the IC device, are searched using a statistical method, such as a Bayesian optimization process, which results in better characteristics of the IC device, such as power, power or area (PPA). A computer system including one or more EDAs configured to perform the method is also disclosed. In addition, the invention also discloses a method and a system for optimizing the physical layout of the integrated circuit device. 一种用于最佳化集成电路装置的实体布局的方法及系统，某些实施例中的方法包括：使用计算机系统，其包括产生EDA工具以产生IC装置的布局；使用诸如贝氏最佳化制程的统计方法来搜寻一或多个输入可变参数，例如IC装置的尺寸及IC装置中电压区域的尺寸，这导致IC装置的较佳特性，例如功率、效能或面积(power,performance or area,PPA)。亦揭示一种计算机系统，其包括经配置以执行方法的一或多个EDA。此外，一种用于最佳化集成电路装置的实体布局的方法及系统亦在此揭露。