SEMICONDUCTOR PACKAGE

The embodiment of the invention provides a semiconductor packaging body. In one embodiment, a semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die includes a first device layer and a first interconnect structure. The semico...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	LI MINGHAN, HONG HANTANG, YANG SHIYI, SUI XIAOLIN
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	LI MINGHAN HONG HANTANG YANG SHIYI SUI XIAOLIN
description	The embodiment of the invention provides a semiconductor packaging body. In one embodiment, a semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die includes a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different from the first circuit design, and the second integrated circuit die includes a second device layer and a second interconnect structure, the second interconnect structure has a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, with the second integrated circuit die surrounded by at least a portion of the substrate. 本公开实施例提供一种半导体封装体。在一个实施例中，半导体封装包括具有第一电路设计的第一集成电路晶粒，且第一集成电路晶粒包括第一装置层和第一内连线结构
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN115101493A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN115101493A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN115101493A3</originalsourceid><addsrcrecordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhqaGBoYmlsaOxsSoAQCabR7Z</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE</title><source>esp@cenet</source><creator>LI MINGHAN ; HONG HANTANG ; YANG SHIYI ; SUI XIAOLIN</creator><creatorcontrib>LI MINGHAN ; HONG HANTANG ; YANG SHIYI ; SUI XIAOLIN</creatorcontrib><description>The embodiment of the invention provides a semiconductor packaging body. In one embodiment, a semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die includes a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different from the first circuit design, and the second integrated circuit die includes a second device layer and a second interconnect structure, the second interconnect structure has a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, with the second integrated circuit die surrounded by at least a portion of the substrate. 本公开实施例提供一种半导体封装体。在一个实施例中，半导体封装包括具有第一电路设计的第一集成电路晶粒，且第一集成电路晶粒包括第一装置层和第一内连线结构</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220923&DB=EPODOC&CC=CN&NR=115101493A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220923&DB=EPODOC&CC=CN&NR=115101493A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LI MINGHAN</creatorcontrib><creatorcontrib>HONG HANTANG</creatorcontrib><creatorcontrib>YANG SHIYI</creatorcontrib><creatorcontrib>SUI XIAOLIN</creatorcontrib><title>SEMICONDUCTOR PACKAGE</title><description>The embodiment of the invention provides a semiconductor packaging body. In one embodiment, a semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die includes a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different from the first circuit design, and the second integrated circuit die includes a second device layer and a second interconnect structure, the second interconnect structure has a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, with the second integrated circuit die surrounded by at least a portion of the substrate. 本公开实施例提供一种半导体封装体。在一个实施例中，半导体封装包括具有第一电路设计的第一集成电路晶粒，且第一集成电路晶粒包括第一装置层和第一内连线结构</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANdvX1dPb3cwl1DvEPUghwdPZ2dHflYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GhqaGBoYmlsaOxsSoAQCabR7Z</recordid><startdate>20220923</startdate><enddate>20220923</enddate><creator>LI MINGHAN</creator><creator>HONG HANTANG</creator><creator>YANG SHIYI</creator><creator>SUI XIAOLIN</creator><scope>EVB</scope></search><sort><creationdate>20220923</creationdate><title>SEMICONDUCTOR PACKAGE</title><author>LI MINGHAN ; HONG HANTANG ; YANG SHIYI ; SUI XIAOLIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN115101493A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LI MINGHAN</creatorcontrib><creatorcontrib>HONG HANTANG</creatorcontrib><creatorcontrib>YANG SHIYI</creatorcontrib><creatorcontrib>SUI XIAOLIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LI MINGHAN</au><au>HONG HANTANG</au><au>YANG SHIYI</au><au>SUI XIAOLIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE</title><date>2022-09-23</date><risdate>2022</risdate><abstract>The embodiment of the invention provides a semiconductor packaging body. In one embodiment, a semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die includes a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different from the first circuit design, and the second integrated circuit die includes a second device layer and a second interconnect structure, the second interconnect structure has a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, with the second integrated circuit die surrounded by at least a portion of the substrate. 本公开实施例提供一种半导体封装体。在一个实施例中，半导体封装包括具有第一电路设计的第一集成电路晶粒，且第一集成电路晶粒包括第一装置层和第一内连线结构</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	chi ; eng
recordid	cdi_epo_espacenet_CN115101493A
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	SEMICONDUCTOR PACKAGE
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T14%3A40%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LI%20MINGHAN&rft.date=2022-09-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN115101493A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true