Stacked vias with bottom portions formed using subtractive patterning

Disclosed herein are methods for fabricating an IC structure, and the resulting IC structure, including stack vias that provide electrical connections between metal lines that metallize different layers of a stack. An example IC structure includes a first metallization layer and a second metallization layer including a bottom metal line and a top metal line, respectively. The IC structure also includes a via having a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (so the via may be referred to as a "stacked via"). A bottom via portion is coupled to and self-aligned with the bottom conductive line, and a top via portion is coupled to and self-aligned with the top conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion may be formed using different manufacturing techniques, such as damascene manufacturing. 本文公开了用于制造IC结构的方法以及所得到的IC结构，该IC结构包括堆叠过孔，该堆叠过孔提供金属化堆叠体的不同层的金属线之间的电连接。示例IC结构包括第一金属化层和第二金属化层，其分别包括底部金属