Integrated chip

The embodiment of the invention relates to an integrated chip. The integrated chip comprises a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and laterally adjacent to the first conductive feature. A recess laterally separates the first conductive member from the second conductive member. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the recess and further extends along opposing sidewalls of the first conductive feature and the second conductive feature. A dielectric cap covers and seals the recess. The dielectric cap has a top surface coplanar with top surfaces of the first conductive feature and the second conductive feature. The first conductive member and the second conductive member include graphene sandwiching one or more metals. 本发明实施例关于一种集成芯片。上述集成芯片包括一基底。一第一导电部件在上述基底的上方。一第二导电部件在上述基底的上方，并横向邻近上述第一导电部件。一凹孔将上述第一导电部件与上述第二导电部件横向分离。一介电衬层沿着上述凹孔的底部从上述第一导电部件延伸至上述第二导电部件且进一步沿着上述第一导电部件与