Memory system

An object of one embodiment is to provide a memory system capable of appropriately transmitting a signal. According to one embodiment, a memory system having a controller, a plurality of memory chips, and a channel is provided. The controller outputs a clock, a timing control signal and a data signal. Each of the plurality of memory chips has at least a clock input terminal, a timing control input terminal, a timing control output terminal, a data input terminal, and a data output terminal. The channel includes a ring bus. The ring bus connects the controller and the plurality of memory chips in a ring shape. The controller transmits a clock signal and a timing control signal to the plurality of memory chips via the channel, and is capable of controlling the operation timing of the memory chips. 一个实施方式的目的是提供一种能够将信号适当地传送的存储器系统。根据一个实施方式，提供一种具有控制器、多个存储器芯片和通道的存储器系统。控制器输出时钟、定时控制信号及数据信号。多个存储器芯片分别至少具有时钟输入端子、定时控制输入端子、定时控制输出端子、数据输入端子、数据输出端子。通道包括环总线。环总线将控制器及多个存储器芯片以环状连接。控制器经由通道将时钟信号及定时控制信号向多个存储器芯片传送，并且能够控制存储器芯片的动作定时。