Communication interface structure between processing die and memory die

The invention provides a communication interface structure for connection between a processing die and a memory die. The communication interface structure comprises the memory die, the processing die and an interconnection route. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnect routes connect the second interface edges of the processing die to the interface groups of the memory die, respectively. 本发明提供一种用于处理管芯与存储器管芯之间连接的通信接口结构，包含存储器管芯、处理管芯以及互连路由。存储器管芯包含第一接口边缘，其中第一接口边缘拆分成多个接口组。处理管芯中的每一个包含第二接口边缘。互连路由分别将处理管芯的第二接口边缘连接到存储器管芯的接口组。