Field programmable gate array (FPGA) adjacent output multiplexer direct connection to minimize routing hops

Methods and apparatus are described that provide direct connection of FPGA adjacent output multiplexers to reduce and potentially minimize routing hops. Embodiments described herein include adding direct connections for output multiplexing from one tile to a neighboring tile. An FPGA device includes a plurality of logical block tiles. The one or more inputs directly connect one or more output multiplexers extending from one or more logical block tiles of the plurality of logical block tiles to one or more adjacent logical block tiles. The one or more direct connections are configured to drive one or more lines starting from one or more neighboring logical block tiles. 描述了提供FPGA相邻输出多路复用器直接连接以减少和潜在地最小化路由跳的方法和设备。本文描述的实施例包括添加从一个瓦片到相邻瓦片的输出多路复用的直接连接。一种FPGA设备包括多个逻辑块瓦片。一个或多个直接连接从多个逻辑块瓦片的一个或多个逻辑块瓦片延伸到一个或多个相邻逻辑块瓦片的输出多路复用器的一个或多个输入端。一个或多个直接连接被配置为驱动起始于一个或多个相邻逻辑块瓦片的一个或多个线。