Semiconductor device
A semiconductor device is disclosed. The semiconductor device includes: a semiconductor substrate including a first region and a second region; a first interlayer insulating layer on the second region; a cap layer disposed on the first interlayer insulating layer, the upper surface of the cap layer...
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creator | LEE WONUL CHOI IN-HYUK YANG JUN-HYUNG |
description | A semiconductor device is disclosed. The semiconductor device includes: a semiconductor substrate including a first region and a second region; a first interlayer insulating layer on the second region; a cap layer disposed on the first interlayer insulating layer, the upper surface of the cap layer including a first trench; conductive patterns spaced apart on the cap layer, side surfaces of the conductive patterns being aligned with inner side surfaces of the first trenches; and a peripheral separation pattern disposed in the first trench to cover a side surface of the conductive pattern. The peripheral separation pattern has a first thickness on a side surface of the conductive pattern, and has a second thickness greater than or equal to the first thickness on a lower surface of the first trench.
公开了一种半导体装置。所述半导体装置包括:半导体基底,包括第一区域和第二区域;第一层间绝缘层,位于第二区域上;盖层,设置在第一层间绝缘层上,盖层的上表面包括第一沟槽;导电图案,在盖层上间隔开,导电图案的侧表面与第一沟槽的内侧表面对齐;以及外围分离图案,设置在第一沟槽中以覆盖导电图案的侧表面。外围分离图案在导电图案的侧表面上具有第一厚度,并且在第一沟槽的下表面上具有大于或等于第一厚度的第二厚度。 |
format | Patent |
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公开了一种半导体装置。所述半导体装置包括:半导体基底,包括第一区域和第二区域;第一层间绝缘层,位于第二区域上;盖层,设置在第一层间绝缘层上,盖层的上表面包括第一沟槽;导电图案,在盖层上间隔开,导电图案的侧表面与第一沟槽的内侧表面对齐;以及外围分离图案,设置在第一沟槽中以覆盖导电图案的侧表面。外围分离图案在导电图案的侧表面上具有第一厚度,并且在第一沟槽的下表面上具有大于或等于第一厚度的第二厚度。</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220826&DB=EPODOC&CC=CN&NR=114944394A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220826&DB=EPODOC&CC=CN&NR=114944394A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE WONUL</creatorcontrib><creatorcontrib>CHOI IN-HYUK</creatorcontrib><creatorcontrib>YANG JUN-HYUNG</creatorcontrib><title>Semiconductor device</title><description>A semiconductor device is disclosed. The semiconductor device includes: a semiconductor substrate including a first region and a second region; a first interlayer insulating layer on the second region; a cap layer disposed on the first interlayer insulating layer, the upper surface of the cap layer including a first trench; conductive patterns spaced apart on the cap layer, side surfaces of the conductive patterns being aligned with inner side surfaces of the first trenches; and a peripheral separation pattern disposed in the first trench to cover a side surface of the conductive pattern. The peripheral separation pattern has a first thickness on a side surface of the conductive pattern, and has a second thickness greater than or equal to the first thickness on a lower surface of the first trench.
公开了一种半导体装置。所述半导体装置包括:半导体基底,包括第一区域和第二区域;第一层间绝缘层,位于第二区域上;盖层,设置在第一层间绝缘层上,盖层的上表面包括第一沟槽;导电图案,在盖层上间隔开,导电图案的侧表面与第一沟槽的内侧表面对齐;以及外围分离图案,设置在第一沟槽中以覆盖导电图案的侧表面。外围分离图案在导电图案的侧表面上具有第一厚度,并且在第一沟槽的下表面上具有大于或等于第一厚度的第二厚度。</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJTs3NTM7PSylNLskvUkhJLctMTuVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfHOfoaGJpYmJsaWJo7GxKgBAF8XIPg</recordid><startdate>20220826</startdate><enddate>20220826</enddate><creator>LEE WONUL</creator><creator>CHOI IN-HYUK</creator><creator>YANG JUN-HYUNG</creator><scope>EVB</scope></search><sort><creationdate>20220826</creationdate><title>Semiconductor device</title><author>LEE WONUL ; CHOI IN-HYUK ; YANG JUN-HYUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN114944394A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE WONUL</creatorcontrib><creatorcontrib>CHOI IN-HYUK</creatorcontrib><creatorcontrib>YANG JUN-HYUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE WONUL</au><au>CHOI IN-HYUK</au><au>YANG JUN-HYUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device</title><date>2022-08-26</date><risdate>2022</risdate><abstract>A semiconductor device is disclosed. The semiconductor device includes: a semiconductor substrate including a first region and a second region; a first interlayer insulating layer on the second region; a cap layer disposed on the first interlayer insulating layer, the upper surface of the cap layer including a first trench; conductive patterns spaced apart on the cap layer, side surfaces of the conductive patterns being aligned with inner side surfaces of the first trenches; and a peripheral separation pattern disposed in the first trench to cover a side surface of the conductive pattern. The peripheral separation pattern has a first thickness on a side surface of the conductive pattern, and has a second thickness greater than or equal to the first thickness on a lower surface of the first trench.
公开了一种半导体装置。所述半导体装置包括:半导体基底,包括第一区域和第二区域;第一层间绝缘层,位于第二区域上;盖层,设置在第一层间绝缘层上,盖层的上表面包括第一沟槽;导电图案,在盖层上间隔开,导电图案的侧表面与第一沟槽的内侧表面对齐;以及外围分离图案,设置在第一沟槽中以覆盖导电图案的侧表面。外围分离图案在导电图案的侧表面上具有第一厚度,并且在第一沟槽的下表面上具有大于或等于第一厚度的第二厚度。</abstract><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRICITY |
title | Semiconductor device |
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