Phase optimization circuit and control method for critical interleaving PFC (Power Factor Correction)
The invention relates to a phase optimization circuit for critical interleaving PFC and a control method, and belongs to the technical field of boosted circuit phase detection, the number of current source circuits is two, a phase detection module comprises a trigger U1 and a trigger U2, the trigger...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention relates to a phase optimization circuit for critical interleaving PFC and a control method, and belongs to the technical field of boosted circuit phase detection, the number of current source circuits is two, a phase detection module comprises a trigger U1 and a trigger U2, the trigger U1 and the trigger U2 are D triggers, and the trigger U1 is connected with the trigger U2. The clock end of the trigger U1 and the clock end of the trigger U2 serve as the input end of the phase detection module, the D pin of the trigger U1 and the D pin of the trigger U2 are jointly connected with the pin of the trigger U1, the pin of the trigger U1 and the pin of the trigger U2 are connected with a voltage source, the pin of the trigger U1 is connected with the Q pin of the trigger U2, and the pin of the trigger U2 is connected with the Q pin of the trigger U2. A pin Q of the trigger U1 is connected with a pin of the trigger U2, the pin Q of the trigger U1 is used as an output end of the digital trigger module, |
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