Interference detection method suitable for FPGA

The invention belongs to the technical field of communication, and particularly relates to an interference detection method suitable for an FPGA (Field Programmable Gate Array). According to the method, the advantages of FPGA pipeline processing are combined, the problem that an interference detection algorithm based on the iteration thought is not beneficial to FPGA implementation is solved, iteration is not needed any more, the interference detection threshold can be determined only by traversing the initial interference data set once, and the interference detection efficiency is improved. The complex control logic that all interference data sets need to be traversed in each iteration during FPGA implementation is avoided, and the processing delay and cache consumption are reduced. 本发明属于通信技术领域，具体的说是一种适用于FPGA的干扰检测方法。本发明结合FPGA流水线处理的优势，解决了基于迭代思想的干扰检测算法不利于FPGA实现的问题，本发明提供的方法不再需要进行迭代，只需遍历一次初始干扰数据集合即可确定干扰检测门限，避免了FPGA实现时每次迭代需遍历所有干扰数据集合的复杂控制逻辑，降低了处理延时和缓存消耗。