Efficient zero-knowledge proof accelerator and method

The invention relates to an efficient zero-knowledge proof accelerator which can provide a high-computing-power and high-efficiency hardware carrier for zero-knowledge proof calculation. According to the method, a fine-grained pipeline architecture is adopted for multi-scalar multiplication, and a plurality of elliptic curve point addition architectures can be integrated into a large-number modular multiplication hardware circuit under the condition that the chip area is not increased, that is, pipeline calculation acceleration can be carried out on elliptic curve point addition calculation only through one large-number modular multiplication hardware circuit. Meanwhile, a plurality of large-number modular multiplication hardware circuits are further integrated, and parallel acceleration can be carried out on point addition calculation of a plurality of elliptic curves. Therefore, compared with the prior art, the method is more flexible and suitable for ASICs and FPGAs of different scales. 本发明涉及一种高效的零知识证明加速器，