INCREASING LUT SPLITTING DEGREE OF FPGA 4-LUT USING EFFECT ADDER

The present invention relates to a field programmable gate array (FPGA) having a 4-LUT (lookup table), the 4-LUT having four stages of a multiplexer. And the 4-LUT can be split. The cleavable 4-LUT includes the ability to implement a plurality of LUTs in an FPGA programmed application as a function in a group including an adder function and other functions. The output of the 4-LUT is exposed to a programmable connection according to FPGA programming. The output of the 4-LUT includes the output of the first multiplexer in the third stage of the 4-LUT, the output of the multiplexer in the second stage, and the output of the multiplexer in the second or third stage. 本发明涉及一种现场可编程门阵列(FPGA)，其具有4-LUT(查找表)，该4-LUT具有多路复用器的四个级。4-LUT可分裂。可分裂的4-LUT包括在FPGA编程的应用中实施多个LUT以作为包括加法器函数和其它函数的组中的函数的能力。4-LUT的输出被暴露于根据FPGA编程的可编程的连接。4-LUT的输出包括4-LUT的第三级中的第一多路复用器的输出、第二级中的多路复用器的输出以及第二级或第三级中的多路复用器的输出。