Daisy chain synchronous Ethernet clock recovery

A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovery clock input, a first recovery clock output, and a first clock multiplexer having a plurality of data inputs, a selection input, and an output coupled to the first recovery clock output, at least one of the data inputs is coupled to a first recovery clock from a respective one of the N network I/O ports, and a first additional data input is coupled to the first external recovery clock input. 一种用于同步以太网系统的PHY芯片包括N个网络输入/输出(I/O)端口、第一外部恢复时钟输入、第一恢复时钟输出以及第一时钟多路复用器，该第一时钟多路复用器具有多个数据输入、选择输入和耦合到该第一恢复时钟输出的输出，该数据输入中的至少一个数据输入耦合到来自N个网络I/O端口中的一个相应网络I/O端口的第一恢复时钟，第一附加数据输入耦合到该第一外部恢复时钟输入。