SEMICONDUCTOR PACKAGE
The invention provides a semiconductor package. Embodiments of the present disclosure provide integrated circuit dies with vertical interconnect features that enable direct connections between vertically stacked integrated circuit dies. Vertical interconnect features may be formed in the sealing rin...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention provides a semiconductor package. Embodiments of the present disclosure provide integrated circuit dies with vertical interconnect features that enable direct connections between vertically stacked integrated circuit dies. Vertical interconnect features may be formed in the sealing ring, which allows for higher routing density than either the interposer or the redistribution layer. Direct connections between vertically stacked integrated circuit dies reduce interposers, redistribution processes, and bump processes in multi-die integration, thereby reducing manufacturing costs.
本公开提出一种半导体封装体。本公开实施例提供具有垂直内连线特征的集成电路裸片,可实现垂直堆叠的集成电路裸片之间的直接连接。垂直内连线特征可形成在密封环中,这允许比中介层或重分布层更高的布线密度。垂直堆叠的集成电路裸片之间的直接连接减少了多裸片整合中的中介层、重分布工艺和凸块工艺,进而降低了制造成本。 |
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