Hopping level vias in metallization layers for integrated circuit devices

An integrated circuit device may be formed that includes an electronic substrate and a metallization structure on the electronic substrate, where the metallization structure includes: a first level including a first dielectric material layer; a second level on the first level, where the second level...

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Bibliographische Detailangaben
Hauptverfasser: LIFF SHAWNA, PASDAST, GREGOR, TIAGELAOUI SAMIR NAZMUL, ELSHERBINI ADEL A, KOBRINSKY MAURO, SWAN JOHANNA
Format: Patent
Sprache:chi ; eng
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Zusammenfassung:An integrated circuit device may be formed that includes an electronic substrate and a metallization structure on the electronic substrate, where the metallization structure includes: a first level including a first dielectric material layer; a second level on the first level, where the second level includes a second dielectric material layer; a third level on the second level, where the third level includes a third dielectric material layer; at least one power/ground structure in the second level; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, where the at least one skip level via comprises a continuous conductive material. 可以形成一种集成电路设备,其包括电子衬底和在电子衬底上的金属化结构,其中,金属化结构包括:第一层级,第一层级包括第一电介质材料层;在第一层级上的第二层级,其中,第二层级包括第二电介质材料层;在第二层级上的第三层级,其中,第三层级包括第三电介质材料层;至少一个电源/接地结构,在第二层级中;以及至少一个跳层级过孔,至少部分