Implementing fully connected neural network layer in hardware

And a full-connection neural network layer is realized in hardware. Methods and data processing systems for implementing one or more fully connected layers of a neural network in hardware are disclosed. According to an embodiment, coefficient data of at least one fully connected layer is loaded into an input buffer of a hardware accelerator, and input data of at least one fully connected layer is loaded into a coefficient buffer of the hardware accelerator. 在硬件中实现全连接神经网络层。公开了用于在硬件中实现神经网络的一个或多个全连接层的方法和数据处理系统。根据实施例，至少一个全连接层的系数数据被加载到硬件加速器的输入缓冲器中，并且至少一个全连接层的输入数据被加载到硬件加速器的系数缓冲器中。