Method and equipment for arranging clock line network in FPGA (Field Programmable Gate Array) chip

The embodiment of the invention provides a method and equipment for arranging a clock net in an FPGA (Field Programmable Gate Array) chip, and the method for arranging the clock net in the FPGA chip comprises the following steps: 1, traversing all clock loads driven by each global clock line, determ...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LI ZUOWEI, YANG QIONGHUA, SUN HAOKAI, XU LIEWEI, WANG SIFEI, YUE YUXIAN
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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