Method and equipment for arranging clock line network in FPGA (Field Programmable Gate Array) chip

The embodiment of the invention provides a method and equipment for arranging a clock net in an FPGA (Field Programmable Gate Array) chip, and the method for arranging the clock net in the FPGA chip comprises the following steps: 1, traversing all clock loads driven by each global clock line, determining a set related to the clock regions in which all the clock loads are located as a division region of the global clock line; step 2, if a clock conflict exists in one clock region, reducing a division region of a global clock line for driving the clock region so that the division region does not include the clock region; and repeating the step 2 until all the clock regions have no clock conflict. According to the technical scheme provided by the embodiment of the invention, the division areas can be reduced so that the division areas do not comprise clock areas with clock conflicts, and thus clock constraints are not violated when the clock load driven by the global clock line is arranged. 本发明实施例提供一种布局FPGA芯片内时钟